The present invention relates to a semiconductor device having a transistor (and particularly to a MIS-type transistor) and a capacitor, particularly to a semiconductor device which is improved in threshold voltage characteristic, and further to a semiconductor device and a semiconductor voltage conversion device.
In recent years, developments have been made to decrease the power source voltage of DRAM memory cells in order to improve reliability and to achieve low power consumption use, so that the difference between a threshold voltage Vth of a memory cell transistor and a cell "1" data write voltage Vcc has been decreased. Such DRAMs have come to cause problems of an increase of leakage between source and drains of a cell transistor due to a drop in threshold voltage and a decrease of a voltage withstanding margin of a gate insulating film due to boosting of a word line.
The problems will be firstly explained with reference to an example of a conventional DRAM memory cell prepared by a combination of a MIS-type transistor (MISFET) and a capacitor, as shown in FIG. 1A.
The memory cell shown in FIG. 1A consists of a capacitor having a plate electrode 6 and a charge storage node 5, and a MISFET having a gate electrode 1 connected to a gate control line 7, an electrode 3 (cited here as a drain electrode) of a source or a drain connected to a data transfer line 8, another electrode 2 (cited here as a source electrode) of a source or a drain connected to a storage node 5, and a substrate electrode 4.
To clarify the problems of a conventional DRAM cell, voltages at respective portions of a memory cell will be denoted by reference symbols as follows. The voltage of the gate control line 7 is denoted as VWL, the voltage of the data transfer line 8 is denoted as VBL, and the voltage of the storage node 5 is denoted as VSN. Indication of potentials at the substrate electrode 4 and the plate electrode 6 will be omitted since electric potentials of these electrodes are normally fixed to constant values in a bulk substrate or a SOI (silicon-on-insulator) substrate having a body contact.
Next, a case of writing data by boosting the storage node to a voltage Vcc will be shown in FIG. 1B. In this case, the voltage of a storage node 5 is lower than a voltage of the data transfer line 8, so that a current flows from the drain electrode 3 to the source electrode 2.
The voltage VWL of the gate control line 7 must be increased to be higher than (Vcc+Vth+.DELTA.Vth) since sufficient writing is carried out until the potential of the storage node reaches Vcc, where the threshold voltage of the cell transistor when VWL=0 V is satisfied is Vth and where an increase of the threshold voltage caused by a substrate bias effect when the voltage between the source and drains increases to Vcc is .DELTA.Vth. However, since the value of VWL is limited by a withstand voltage of a gate insulating film, Vth should be set to be low in order to restrict VWL also to be low.
If data is written with the voltage of the storage node 5 lowered to 0 V, no increase .DELTA.Vth of the threshold voltage is caused by a substrate bias effect as described above, and therefore, the problem as described above is not so serious compared to a case of writing data with the voltage of the storage node 5 boosted to the voltage of Vcc.
Next, consideration is taken into a leakage current where the electric potential of the gate control line 7 is lowered and the cell transistor is turned off, to maintain a data holding state. Since the potential of the gate control line 7 is normally set to 0 V, VWL=0 V is indicated in FIGS. 1C and 1D for conveniences. If there is a potential difference between the storage node 5 and the data transfer line 8, a sub-threshold current I.sub.leak of the transistor flows between the source and drain of the transistor.
Further, consideration is taken into a case of setting the potential VBL of the data transfer line 8 to 0 V where "1" has previously been written into the cell to obtain VSN to Vcc (in FIG. 1C). This case occurs when data "0" is written into another memory cell connected to the same data transfer line 8 as a target cell. In this case, a sub-threshold current I.sub.leak flows from the storage node 5 to the data transfer line 8, thereby decreasing the potential of the storage node 5, resulting in a problem that a sufficient voltage amplitude is not obtained when reading data. In this case, it is preferable to increase Vth since the sub-threshold current I.sub.leak decreases if the gate voltage VWL is decreased to be smaller in comparison with the threshold voltage Vth.
This problem of sub-threshold current also occurs where "0" has previously been written in a cell and the potential VBL of the data transfer line is set to Vcc as shown in FIG. 1D. However, the present inventors has found that a problem occurs less frequently in the case of FIG. 1D than the case of FIG. 1C.
In case of FIG. 1C, a current flows out into the data transfer line 8 from the storage node 5 by I.sub.leak, and the potential VSN of the storage node 5 is lowered to (Vcc-dV) from Vcc. In this state, the potential of the data transfer line 8 increases by dV.Cs/CB. Normally, a data transfer line of a DRAM has a capacitance CB greater than the capacitance Cs of the storage node Cs, so that the potential of the data transfer line changes by a small change amount. The substrate bias effect is decided by the potential of the data transfer line 8 having a lower voltage than the storage node 5, i.e., by an increase dV.Cs/CB, so that the sub-threshold leakage current keeps flowing.
Meanwhile, in the case of FIG. 1D, a current flows into the storage node 5 from the data transfer line 8 due to I.sub.leak, and the potential VSN of the storage node increases to +dV from 0. In this case, the charge change amount is dV.Cs and is equal to the value indicated in FIG. 1C. However, the potential of the data transfer line 8 decreases by dV.Cs/CB where the capacitance of the storage node of the cell is Cs, unlike the case of FIG. 1D. In this state, the substrate bias effect is decided by the potential of the storage node 5 having a voltage lower than the data transfer line 8, i.e., by an increase dV. The increase dV is greater than the increase dV.Cs/CB shown in FIG. 1C and the threshold voltage increases due to the substrate bias effect depending on the increase dV, so that the sub-threshold leakage current stops flowing in.
As described above, the threshold voltage Vth must be restricted to be low in order to write data "1" into a cell, while the threshold voltage Vth must be maintained high in order to restrict a sub-threshold leakage current from a cell. This leads to a problem that two desirable conditions are thus required for the threshold voltage. This problem appears conspicuously in a DRAM of a low power source voltage operation which cannot maintain a sufficient difference between an amplitude Vcc of a writing voltage and a threshold voltage Vth.
A similar problem occurs in a memory using a ferroelectric capacitor in which the voltage of a plate electrode 6 is set to a so-called (1/2)Vcc when holding data. The structure of a memory cell is similar to the above as long as a ferroelectric film is used as a capacitor insulating film, and explanation thereof will be omitted herefrom. In a ferroelectric capacitor in which the voltage of a plate electrode 6 is set to (1/2)Vcc, when the storage node voltage of a cell in which "1" has been written changes from Vcc to 0 V by a sub-threshold leakage current, as shown in FIG. 1, the direction of an electric field applied between the plate electrode 6 and the storage node 5 is inverted, i.e., a so-called polarization inversion occurs and the data in the memory cell is broken.
Further, a similar problem occurs in a charge pump circuit. FIGS. 2A to 2C show basic units of a charge pump circuit consisting of a capacitor and a MISFET. The capacitor has a plate electrode 6 and a charge capacitance electrode 5. The MISFET comprises an electrode 3 (cited here as a drain electrode) as one of a source and a drain connected to an output end, and another electrode 2 (cited here as a source electrode) as the other of the source and drain, and a gate 1 connected together with the electrode 2 to the storage node 5. Further, the plate electrode 6 is alternately connected periodically to a plurality of voltage sources having two different voltages V1 and V2, by and element as a switch.
A conventional charge pump circuit has a problem as explained below.
In a charge pump circuit, basically, two power sources V1 and V2 are alternately connected so that electric charges are moved in a direction from the source electrode 2 to the drain electrode 3, thereby to obtain a potential difference between the electrodes 2 and 3. FIGS. 2A to 2C show a case in which the voltage of the drain electrode 3 is boosted in comparison with the voltage of the source electrode 2.
FIG. 2A shows a case in which the plate voltage is switched from the voltage source V2 to the voltage source V1. Here, since the voltage V1 is higher than the voltage V2, the plate potential increases. Accordingly, the potential of the storage node 5 increases and the voltage of the gate electrode 1 increases by about (V1-V2), to be higher than a threshold voltage Vth. As a result, the transistor is turned on and electric charges stored in the storage node 5 is transferred to the drain electrode 3. Where the potential of the storage node 5 turned on is VSN, the potential of the drain electrode 3 is VSN-Vth. In order to restrict a decrease of VSN-Vth, the threshold voltage Vth should preferably be low.
Next, FIG. 2B shows a case in which the plate voltage is switched from the voltage source V1 to the voltage source V2. In this case, since the voltage V2 is lower than the voltage V1, the plate potential decreases. Accordingly, the potential of the storage node 5 decreases by about (V1-V2) and the voltage of the gate electrode 1 decreases to be equal to or lower than Vth. As a result, the transistor is turned off. Here, a sub-threshold current flows from the drain electrode 3 to the source electrode 2 in a direction opposite to that when the transistor is turned on, i.e., in a direction opposite to the direction in which electric charges are transferred in FIG. 2A, thereby causing a loss of transferred charges. In order to restrict the loss of transferred charges, the threshold voltage Vth of the transistor should preferably be high.
From above, the threshold voltage Vth must be restricted to be low in order to prevent a voltage drop when the transistor is turned on, while the threshold voltage Vth must be maintained to be high in order to restrict a loss of transferred charges caused by a sub-threshold leakage through a transistor. There is a problem that two different conditions are thus required for a threshold voltage. This problem appears conspicuously in a booster circuit and a negative voltage generator circuit, operated by a low power source voltage by which a sufficient difference cannot be maintained between an amplitude Vcc of a writing voltage and a threshold voltage Vth.
FIG. 2C shows an example of a negative voltage generator circuit in which a voltage oscillator circuit is used in place of power sources V1 and V2. More specifically, two MISFETs each having a gate and a source connected together are connected in series with each other, and the end of a drain electrode 3 of this serial connection is connected to a ground end (0 V) as an input while the end of a source electrode 2 thereof is connected to an output end. A connection point between transistors is connected to a voltage oscillator circuit through a capacitor. This kind of negative voltage generator circuit also uses a charge pump circuit and therefore has a similar problem.
As a result of developments and studies made by the present inventors, the following problem has been revealed.
In a conventional semiconductor memory device using a memory cell, such as a DRAM or the like, the threshold voltage Vth must be restricted to be low in order to maintain a sufficient cell writing current while the threshold voltage Vth must be maintained to be high in order to restrict a sub-threshold leakage current from a cell. A problem thus lies in that two contradictory requirements must be satisfied for the threshold voltage.
In a charge pump circuit, also, the threshold voltage Vth must be restricted to be low in order to restrict a voltage drop when a transistor is turned on while the threshold voltage Vth must be maintained to be high in order to restrict a loss of transferred charges caused by a sub-threshold leakage. A problem thus lies in that two contradictory requirements must also be satisfied for the threshold voltage.